This invention relates to integrated circuits, and more particularly, to Dynamic Random Access Memory (DRAM) and Insulated Gate Field Effect Transistors (IGFETs) in which vertical transistors are used with gate connections formed by a Damascene process and bit line region contacts which are self-aligned and borderless to adjacent gates. An IGFET may also be denoted as a Metal-Oxide-Semiconductor (MOS) transistor.
Many chip fabricators (fabs) use planar structures to form DRAMS with polysilicon (poly) and tungsten silicide (WSiX) for gate conductors. As ground rules become tighter (e.g., =0.13 xcexcm) it is increasingly more difficult to maintain feature sizes of 1F using these processes and to provide void free insulation between gates of transistors. In general Critical Dimension (CD) tolerances shrink less aggressively than ground rules and therefore even small changes within process tolerances can result in product failure. Conventional sidewall gate insulation layers are typically formed after the formation of a gate electrode of a transistor. The aspect ratio of the opening through which these conventional sidewall spacers are formed is typically relatively high. This can result in formation of elongated voids in the insulation material between the gates.
If Boron Phosphosilicate Glass (BPSG) is used as one of the isolation materials, voids can be formed along the wordline which can inadvertently be filled with a conductive material which could lead to an undesirable short connection. Even relatively short etching times for precleaning the substrate surface prior to the Bitline contact fill with conductive material may result in the formation of pathways to the adjacent contact conductor producing electrical short circuits in the arrays.
Planar Gate transistor technology relies on the deposition of conducting materials which are patterned using photolithographic methods. After the conductor layers are patterned, it is necessary to isolate them from each other. For high aspect ratio films and aggressive ground rules in which critical dimension tolerances do not scale as fast as ground rules, it is becoming increasingly more difficult to fill the gaps with an insulating material with a low thermal budget. For example, if the gap is 150 nm and the layer thickness is 1100 nm, the aspect ratio of the feature to fill becomes larger than seven. It is not uncommon during the deposition of the gap fill material to have the gap fill first above the base which precludes achieving a complete gap fill and leaves the unfilled portion of the gap without isolation. Critical dimension control of the conducting material becomes less stringent when vertical field effect transistors are used in the memory cells of the DRAM. Thus a Damascene process can be used without any substantial loss in yield.
In the vertical DRAM cell the effective gate length can be decoupled from the lateral photographic dimensions. The stringent leakage requirements of the DRAM cell are limited by the scaling methods now in use. A cascade of problems arise as the gate poly length is reduced. For example, a reduction in gate poly length requires thinner gate oxides and increased channel doping to prevent short channel effects. When the doping levels are increased, the junction leakage can effect the data retention time.
It is desirable to be able to fabricate memory cells that include vertical insulated gate field effect transistors and trench capacitors and to be able to obtain high density at high yields and to fill contact openings which have large aspect ratios while achieving acceptable yields.
In a first aspect the invention is a method of forming in a semiconductor body of a first conductivity type in which there has been formed an array of memory cells which each comprise an insulated gate field effect transistor, which comprises first and second output regions of a second opposite conductivity type and a gate which is separated from the semiconductor body by a gate dielectric layer, contacts to the gates and first output regions. The method comprises the steps of: forming first insulating regions around portions of a top surface of the semiconductor body in which gate contacts are to be formed; forming gate contacts using a Damascene process in the portions of the semiconductor body surrounded by the first insulating regions; forming second insulating regions around exposed portions of the gate contacts; forming a borderless contact to each one of the first output regions of each transistor with the first and second insulating regions electrically isolating the gate contacts from the contacts to the first output regions.
In a second aspect the invention is a method of forming in a semiconductor body, which has a top surface and being of a first conductivity type, and in which there has been formed an array of memory cells which each comprise a vertical insulated gate field effect transistor having first and second output regions of a second opposite conductivity type and a gate which is separated from a vertical surface of the semiconductor body by a gate dielectric layer, contacts to the gates and the first output regions. The method comprises the steps of: forming vertical insulating regions around portions of the top surface of the semiconductor body in which gate contacts are to be formed; forming gate contacts using a Damascene process in the portions of the semiconductor body surrounded by the first insulating regions; forming horizontal insulating regions around exposed portions of the gate contacts; forming a borderless contact to each one of the first output regions of each transistor with the vertical and horizontal insulating regions electrically isolating the gate contacts from the contacts to the first output regions.
In a third aspect the invention is a method of forming in a semiconductor body, which has a top surface and is of a first conductivity type, and in which there have been formed an array of memory cells which each comprise a trench capacitor and a vertical insulated gate field effect transistor, which comprises first and second output regions of a second opposite conductivity type and a gate which is separated from a vertical surface of the semiconductor body by a gate dielectric layer, electrical contacts to the gates and first output regions. The method comprises the steps of: forming a first insulating layer over a top surface of the semiconductor body; forming first openings through the first insulating layer so as to expose a portion of the top surface of the semiconductor body in which the gates are located; forming insulating sidewall spacer regions on sidewalls of the openings through the first insulating layer with the insulating sidewall spacer regions being of a different material than the first insulating layer; over filling the first openings through the first insulating layer with a first conductor which contacts the gates of each transistor and extends over a top surface of the first insulating layer; removing portions of the first conductor on the top surface of the first insulating layer so as to result in a segmented first conductor filling each of the first openings; covering exposed surfaces of the first conductors with a second insulating layer which is of a material different than that of the first insulating layer; forming first openings through the second insulating layer and second openings through the first insulating layer between adjacent insulating sidewall spacer regions to expose portions of the semiconductor top surface which include portions of the first output regions; and filling each of the second openings through the first insulating layer with a second conductor which contacts a first output region such that each second conductor is self aligned and borderless.
In a fourth aspect the invention is a method of forming in a semiconductor body of a first conductivity type in which there have been formed an array of memory cells which each comprise a trench capacitor and a vertical insulated gate field effect transistor, which comprises first and second output regions of a second opposite conductivity type and a gate which is separated from a surface of the semiconductor body by a gate dielectric layer, electrical contacts to the gate and first output region. The method comprises the steps of: forming a first insulating layer over a top surface of the semiconductor body; forming separated first openings through the first insulating layer so as to expose a portion of the top surface of the semiconductor body in which the gates are located; forming insulating sidewall spacer regions on sidewalls of the openings through the first insulating layer with the insulating sidewall spacer regions being of a different material than the first insulating layer; over filling the first openings through the first insulating layer with a first conductor which contacts the gates of each transistor and extends over a top surface of the first insulating layer; removing portions of the first conductor on the top surface of the first insulating layer so as to result in a segmented first conductor filling each of the first openings; removing portions of the segmented first conductors so as to recess same in each of the first openings; over filling the first openings with a second insulating layer which is of a material different than that of the first insulating layer; removing portions of the second insulating layer so as to form a planar surface which includes portions of the first and second insulating layers; forming second openings through the first insulating layer between adjacent insulating sidewall spacers to expose portions of the semiconductor top surface which include portions of the first output regions; and filling each of the second openings through the first insulating layer with a second conductor which contacts a first output region such that each second conductor is self aligned and borderless.
In a fifth aspect the invention is a method of forming in a semiconductor body of a first conductivity type in which there have been formed an array of memory cells which each comprise a trench capacitor and a vertical insulated gate field effect transistor, which comprises first and second output regions of a second opposite conductivity type and a gate which is separated from a surface of the semiconductor body by a gate dielectric layer, electrical contacts to the gate and first output region. The method comprises the steps of: forming a first insulating layer over a top surface of the semiconductor body; forming separated first openings through the first insulating layer so as to expose a portion of the top surface of the semiconductor body in which the gates are located; forming insulating sidewall spacer regions on sidewalls of the openings through the first insulating layer with the insulating sidewall spacer regions being of a different material than the first insulating layer; over filling the first openings through the first insulating layer with a first conductor which contacts the gates of each transistor and extends over a top surface of the first insulating layer; removing portions of the first conductor on the top surface of the first insulating layer so as to result in a segmented first conductor filling each of the first openings; removing portions of the segmented first conductors so as to recess same in each of the first openings; over filling the first openings with a second conformal insulating layer which is of a material different than that of the first insulating layer; filling recesses in the second conformal insulating layer with a self planarizing third insulator layer so as to form a planar surface common to the second conformal insulating layer and the self planarizing insulator layer, the self planarizing insulator layer being of a different material than the first insulating layer; removing portions of the second conformal insulating layer not covered by the self planarizing third insulating layer; removing the self planarizing third insulator layer; forming a fourth insulating layer over the resulting structure; removing all portions of the fourth insulating layer except those portions which are over the remaining portions of the second insulating layer and remaining portions of the first insulator layer to create separated first openings through the fourth insulator layer and second openings through the first insulator layer to expose portions of the top surface of the semiconductor body in which are located the first output regions, the first openings through the fourth insulating layer and the second openings through the first insulating layer being aligned; filling each of the first openings through the fourth insulating layer and the second openings through the first insulating layer with a second conductor which contacts a first output region such that each second conductor is self aligned and borderless.
The invention will be better understood from the following more detailed description taken in conjunction with the accompanying drawings and claims.